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 C8051F132
100 MIPS, 64 kB Flash, 10-Bit ADC, 100-Pin Mixed-Signal MCU
Analog Peripherals
10-Bit ADC
High-Speed 8051 C Core
-
-
1 LSB INL; no missing codes Programmable throughput up to 100 ksps 8 external inputs; programmable as single-ended or differential Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5 Data-dependent windowed interrupt generator Built-in temperature sensor (3 C)
Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Up to 100 MIPS throughput with 100 MHz system clock 16 x 16 multiply/accumulate engine (2-cycle) 8448 bytes data RAM 64 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes are reserved) External parallel data memory interface 64 port I/O; all are 5 V tolerant Hardware SMBusTM (I2CTM compatible), SPITM, and two UART serial ports available concurrently Programmable 16-bit counter/timer array with six capture/compare modules 5 general-purpose 16-bit counter/timers Dedicated watchdog timer; bidirectional reset Real-time clock mode using timer 3 or PCA Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation On-chip programmable PLL: up to 100 MHz External oscillator: Crystal, RC, C, or Clock Typical operating current: 50 mA at 100 MHz Typical stop mode current: 0.4 A
Memory
Two Comparators Internal Voltage Reference VDD Monitor/Brown-out Detector
On-Chip JTAG Debug & Boundary Scan
Digital Peripherals
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On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required) Provides breakpoints, single stepping, watchpoints, stack monitor Inspect/modify memory and registers Superior performance to emulation systems using ICE-chips, target pods, and sockets IEEE1149.1 compliant boundary scan
Clock Sources
Supply Voltage: 3.0 to 3.6 V
100-Pin TQFP Temperature Range: -40 to +85 C
VDD VDD VDD DGND DGND DGND AV+ AV+ AGND AGND TCK TMS TDI TDO RST
Digital Power
Port I/O Config. UART0 P0 Drv
P0.0 P0.7
SFR Bus
Analog Power
UART1 SMBus
JTAG Logic
Boundary Scan Debug HW
Reset
MONEN
VDD Monitor
WDT
8 0 5 1 C o r e
256 byte RAM 8kbyte XRAM External Data Memory Bus
SPI Bus PCA Timers 0, 1, 2, 4 Timer 3/ RTC P0, P1, P2, P3 Latches Crossbar Config.
C R O S S B A R
P1 Drv
P1.0/AIN2.0 P1.7/AIN2.7
P2 Drv
P2.0 P2.7
P3 Drv
P3.0 P3.7
XTAL1 XTAL2
External Oscillator Circuit PLL Circuitry Calibrated Internal Oscillator
System Clock
VREF
VREF
FLASH 64kbyte
P4.0
Bus Control
VREF0 AIN0.0 AIN0.1 AIN0.2 AIN0.3 AIN0.4 AIN0.5 AIN0.6 AIN0.7 CP0+ CP0CP1+ CP1-
64x4 byte cache
A M U X
C T L
P4 Latch
P4 DRV
P4.4 P4.5/ALE P4.6/RD P4.7/WR P5.0/A8 P5.7/A15 P6.0/A0 P6.7/A7
Prog Gain
ADC 100ksps (10-Bit)
Address Bus
A d d r D a t a
P5 Latch P6 Latch
P5 DRV P6 DRV
TEMP SENSOR
Data Bus
P7 Latch
CP0 CP1
P7 DRV
P7.0/D0 P7.7/D7
General Purpose
Copyright (c) 2004 by Silicon Laboratories
8.9.2004
C8051F132
100 MIPS, 64 kB Flash, 10-Bit ADC, 100-Pin Mixed-Signal MCU Selected Electrical Specifications
(TA = -40 to +85 C, VDD = 3.0 V unless otherwise specified)
PARAMETER CONDITIONS GLOBAL CHARACTERISTICS Supply Voltage Supply Current Clock = 100 MHz (CPU active) Clock = 1 MHz Clock = 32 kHz Supply Current Oscillator off; VDD Monitor Enabled (shutdown) Oscillator off; VDD Monitor Disabled Clock Frequency Range INTERNAL CLOCKS Oscillator Frequency PLL Frequency A/D CONVERTER Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Signal-to-Noise Plus Distortion Throughput Rate MIN 3.0 -- -- -- -- -- DC 24.0 -- -- -- 59 -- TYP -- 50 0.6 16 10 0.4 -- 24.5 -- 10 -- -- -- -- MAX 3.6 -- -- -- -- -- 100 25.0 100 1 1 -- 100 UNITS V mA mA A A A MHz MHz MHz bits LSB LSB dB ksps
Package Information
D D1
C8051F120DK Development Kit
MIN NOM MAX (mm) (mm) (mm) A 1.20 0.15
A1 0.05
A2 0.95 1.00 1.05 b D
E1 E
0.17 0.22 0.27 16.00 14.00 0.50 16.00 14.00 -
D1 e E E1
100 PIN 1 DESIGNATOR
1 e A b A1
A2
General Purpose
Copyright (c) 2004 by Silicon Laboratories
8.9.2004
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders


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